Semiconductor devices are specified (spec'ed) to operate within certain parameters, such as a maximum power draw and a maximum clock frequency. While semiconductor manufacturing processes are very precise, process variations do occur. Although the manufacturing process may target a typical device, sometimes process variations produce slower chips or faster chips. As device sizes shrink, larger relative variations may occur.
Chips may be tested to determine their power draw and speed, and these chips may be sorted into slow-chip bins, fast-chip bins, and typical-chip bins. The faster chips may be sold as faster speed grades, while the slower chips may be sold for slower speed grades. Unfortunately, such process skews are not always reproducible or planned but may occur randomly, making for logistical difficulties. Therefore all process skews are often lumped together. The slowest expected process skews determine the specified speed of the device, while the fastest expected process skews determine the specified maximum power dissipation.
FIG. 1 is a graph showing how process variations affect device specifications. The slowest process skew (SS) has the lowest power and the lowest performance or speed. A typical process (TT) has a better power and performance product. The fastest process skew (FF) has the highest performance and speed, but also consumes the most power.
All three process skews—slow, typical, and fast, share the same device specifications when no grade sorting is performed. Devices produced with the slowest process determine the speed specs such as the maximum clock frequency, or the minimum clock-to-output delay times. However, the fast devices consume more power than do the slower devices, so power specs are determined by devices manufactured by the fast process skews. The power-supply voltage VDD is usually fixed.
The performance and power specs are determined by the worst-case devices over the expected process skews. Slow devices set the speed specs and fast devices set the power specs. This is not optimal, since fast devices are spec'ed slower than they can actually operate, and slow devices actually draw less power than spec'ed.
Specialized sensors may be added to chips to facilitate at-speed testing. Dummy bit lines have been added to RAM arrays to adjust bit-line sensing circuits. An oscillator or a canary circuit may be added to track process variations. However, the actual circuit may be much more complex than an oscillator, resulting in tracking errors. For logic chips, a dummy path and an on-chip timing sensor may be added. The timing sensor can report its results to a tester or even to an on-chip controller that can adjust operating conditions, such as to slow down or stop a clock to reduce power consumption.
Actual critical paths may be used during normal chip operation to detect timing failures. However, there may be few transitions during long periods of time of normal chip operation. Some critical paths may not transition for many seconds or minutes, and some may not transition at all for very long periods of time. Sensing timing failures cannot occur without transitions that pass through the critical paths.
Test modes may also be used to test critical paths. However, the test modes may have significant overhead. Test data may need to be scanned in serially to a long chain of registers, then the critical path tested, and then results serially scanned out of a long chain of registers before the results are available. Again, a long delay occurs before sensor results may be used to adjust operating conditions. This time lag is undesirable.
What is desired is to ensure that many transitions occur in a critical path to allow for sensing of timing failures. It is desired to replicate critical paths and apply test patterns to these critical paths to ensure a high transition density. It is desired to use the sensing results to adjust VDD to compensate for the actual temperature, process, and voltage conditions of the replicated critical path. It is also desired to use both replicated critical paths and representational critical paths.